Prevent Overbuilding and secure your design with the FPGA Lock IP
The FPGA Lock is a small FPGA IP core that prevents overbuilding and cloning of your FPGA-based systems and consequently protects your revenue. It can also be used to guarantee hardware integrity in Safety Critical, Medical or Military/Defence applications.
The IP core uses less than 1 kLUT FPGA resources, one user IO and hardly any PCB realestate. It is intended to communicate with Microchip‘s ATSHA204A hardened crypto authenti- cation IC. Users can prevent IP theft and Overbuilding.
The FPGA Lock IP uses symmetric cryptography, meaning the FPGA Lock IP and the crypto chip share a common secret key.
Free Evaluation with T*Square Educations Boards!
| Article | Description | Price |
|---|---|---|
| FPGA-LOCK-EVAL | Encrypted source files. The secret key is used for evaluation only. | 0,- € |
| FPGA-LOCK-FIX | Encrypted source files. The secret key is used for production only. No MOQ for crypto chip. | 1.000,- € |
| FPGA-LOCK-CUST | Encrypted source files. The customer specific secret key is used for just one customer, but it is unknown to this customer. MOQ for crypto chip. | 2.000,- € |
| FPGA-LOCK-RTL | RTL source files. Customer has full control over the secret key. | 7.500,- € |
- Test triggered, core Reads device ID.
- Core sends 256 bit random challenge.
- ATSHA204a perfoms SHA256 hash on the challenge, its ID and a programmed 256 bit secret key. The hash result is returned to the core.
- The core also performs the hash on the challenge, device ID and secret key (that it knows).
- If the two sets of hash results match then a device with the correctly programmed secret key is present, FPGA functionality is enabled