Efinix has released its second generation Sapphire RISC-V core. It is available from TRS-STAR GmbH together with the FPGA devices and development software. It is fully configurable via a graphical user interface. The 32-bit core has customised instruction functions for highly accelerated workloads. The Sapphire is compatible with both the Efinix Titanium^® and Trion^® FPGAS families. It is also Linux compatible with a memory management unit and offers an optional memory controller for DDR or HyperRAM.

RISC-V is an open source standard instruction set architecture (ISA) managed by the non-profit RISC-V Foundation. The modular ISA has a base instruction set and optional extension sets. RISC-V is open source and free of charge. There are currently over 65 RISC-V cores available, both commercial and open source.

RISC-V SoCs from Efinix are based on the VexRiscv core. This core is a 32-bit CPU that uses the ISA RISCV32I with I, M ,A, F and D extensions. It has the five pipeline stages of fetch, decode, execute, store and write back and a configurable function set. The SoC has a RISC-V processor, memory, a number of input and output units and interfaces for embedded user functions. This makes it easy to create entire systems with embedded computing functions and custom accelerators, all housed in the same Titanium^® or Trion^® FPGA.

Efinix ships a package of hardware and software files with each RISC-V SoC. To assist in the development of software applications, Efinix provides a collection of pre-compiled open source software. These packages can be used to create RTL designs based on a sample design for an Efinix development board and can be extended for custom applications. The software development environment can be set up using a sample project and own software can be created based on sample projects. The API provided can be used for this. The Software Development Kit includes an Eclipse IDE for managing projects as well as software, a GCC compiler and an OpenOCD debugger.